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MC74HC374A Octal 3-State Non-Inverting D Flip-Flop
High-Performance Silicon-Gate CMOS
The MC74HC374A is identical in pinout to the LS374. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Data meeting the setup time is clocked to the outputs with the rising edge of the clock. The Output Enable input does not affect the states of the flip-flops, but when Output Enable is high, the outputs are forced to the high-impedance state; thus, data may be stored even when the outputs are not enabled. The HC374A is identical in function to the HC574A which has the input pins on the opposite side of the package from the output. This device is similar in function to the HC534A which has inverting outputs.
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20 PDIP-20 N SUFFIX CASE 738 1 1 20 20 1 SOIC-20 DW SUFFIX CASE 751D 1 74HC374A AWLYYWWG MC74HC374AN AWLYYWWG
20
* * * * * * * *
Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 266 FETs or 66.5 Equivalent Gates Pb-Free Packages are Available*
20 20 1 TSSOP-20 DT SUFFIX CASE 948E 1 HC 374A ALYWG G
20 1
20 SOEIAJ-20 F SUFFIX CASE 967 1
74HC374A AWLYWWG
A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = Pb-Free Package G = Pb-Free Package (Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
1
July, 2005 - Rev. 10
Publication Order Number: MC74HC374A/D
MC74HC374A
PIN ASSIGNMENT
OUTPUT ENABLE Q0 2 5 6 9 12 15 16 19 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 NONINVERTING OUTPUTS D0 D1 Q1 Q2 D2 D3 Q3 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CLOCK
LOGIC DIAGRAM
D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 CLOCK 3 4 7 8 13 14 17 18 11
FUNCTION TABLE
OUTPUT ENABLE 1 PIN 20 = VCC PIN 10 = GND Inputs Output Enable L L L H Clock D H L X X Output Q H L No Change Z
L,H, X
X = don't care Z = high impedance
ORDERING INFORMATION
Device MC74HC374AN MC74HC374ANG MC74HC374ADW MC74HC374ADWG MC74HC374ADWR2 MC74HC374ADWR2G MC74HC374ADT MC74HC374ADTG MC74HC374ADTR2 MC74HC374ADTR2G MC74HC374AF MC74HC374AFG MC74HC374AFEL MC74HC374AFELG Package PDIP-20 PDIP-20 (Pb-Free) SOIC-20 WIDE SOIC-20 WIDE (Pb-Free) SOIC-20 WIDE SOIC-20 WIDE (Pb-Free) TSSOP-20* TSSOP-20* TSSOP-20* TSSOP-20* SOEIAJ-20 SOEIAJ-20 (Pb-Free) SOEIAJ-20 SOEIAJ-20 (Pb-Free) Shipping 18 Units / Box 18 Units / Box 38 Units / Rail 38 Units / Rail 1000 Tape & Reel 1000 Tape & Reel 75 Units / Rail 75 Units / Rail 2500 Tape & Reel 2500 Tape & Reel 40 Units / Rail 40 Units / Rail 2000 Tape & Reel 2000 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC74HC374A
II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I II II I I IIIIIIIIIIIIIIIIIIIII I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIII I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I I I IIIIIIIIIIIIIIIIIIIIIII III II II IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII I I I I I IIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I
IIIIIIIIIIIIIIIIIIII I I I I III III II I I I I I I I I I IIIIIIIIIIIII III I I II I I I I I I I IIIIIIIIIIIII III I I I I I IIIIIIIIIIII I II I I I I I I I IIIIIIIIIIIII III I I I III I I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I IIIIIIIIIIIII III I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I I I I IIIIIIIIIIIII III I I I I I IIIIIIIIIIIII III I I I I I I I I I IIIIIIIIIIIIIIII IIII IIIIIII I IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS
SymbolIIIIIIIIIIIIII Parameter VCC Vin DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) Value Unit - 0.5 to + 7.0III V V V - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 35 75 750 500 450 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP SOIC Package TSSOP Package mW Tstg TL Storage Temperature - 65 to + 150 260 _C _C Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC, SSOP or TSSOP Package)
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V V
DC Supply Voltage (Referenced to GND)
Vin, Vout TA
DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1)
VCC
- 55 0 0 0
+ 125 1000 500 400
_C ns
tr, tf
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit v 85_C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 1.90 4.40 5.90 2.34 3.84 5.34 0.10 0.10 0.10 0.33 0.33 0.33
Symbol VIH
Parameter
Test Conditions
VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0
- 55 to 25_C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 1.90 4.40 5.90 2.48 2.98 5.48 0.10 0.10 0.10 0.26 0.26 0.26
v 125_C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 1.90 4.40 5.90 2.20 3.70 5.20 0.10 0.10 0.10 0.40 0.40 0.40
Unit V
Minimum High-Level Input Voltage
Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 mA
VIL
Maximum Low-Level Input Voltage
Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 mA
V
VOH
Minimum High-Level Output Voltage
Vin = VIH or VIL |Iout| v 20 mA Vin = VIH or VIL
V
|Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA
V V
VOL
Maximum Low-Level Output Voltage
Vin = VIH or VIL |Iout| v 20 mA Vin = VIH or VIL
|Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA
V
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MC74HC374A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I
Guaranteed Limit v 85_C 1.0 5.0 Symbol Iin IOZ Parameter Test Conditions VCC V 6.0 6.0 - 55 to 25_C 0.1 0.5 v 125_C 1.0 10 Unit mA mA Maximum Input Leakage Current Maximum Three-State Leakage Current Vin = VCC or GND Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND Iout = 0 mA ICC Maximum Quiescent Supply Current (per Package) 6.0 4 40 160 mA NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
II I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I II I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I II I I IIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I
Guaranteed Limit v 85_C 5 10 24 28 Symbol fmax Parameter VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 - 55 to 25_C 6 15 30 35 v 125_C 4 8 20 24 Unit Maximum Clock Frequency (50% Duty Cycle) MHz tPLH tPHL Maximum Propagation Delay, Input Clock to Q (Figures 1 and 5) 125 80 25 21 150 100 30 26 150 100 30 26 75 27 15 13 10 15 155 110 31 26 190 125 38 33 190 125 38 33 95 32 19 16 10 15 190 130 38 32 225 150 45 38 225 150 45 38 110 36 22 19 10 15 ns tPLZ tPHZ Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) ns tPLZ tPHZ Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) ns tTLH tTHL Maximum Output Transition Time, Any Output (Figures 1 and 5) ns Cin Maximum Input Capacitance pF pF Cout Maximum Three-State Output Capacitance (Output in High-Impedance State) NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V 34
2f
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
CPD
Power Dissipation Capacitance (Per Enabled Output)*
pF
* Used to determine the no-load dynamic power consumption: PD = CPD VCC ON Semiconductor High-Speed CMOS Data Book (DL129/D).
+ ICC VCC . For load considerations, see Chapter 2 of the
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II I I I I I I I I IIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIII I IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIII I I IIIIIII IIIII I I II III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol tr, tf tsu tw th Maximum Input Rise and Fall Times Minimum Pulse Width, Clock Minimum Hold Time, Clock to Data Minimum Setup Time, Data to Clock Parameter
CLOCK
Q
50% 10%
90%
10%
90% 50%
tr
tW
tPLH
tTLH
Figure 1.
1/fmax
tf
tPHL
tTHL
CLOCK
DATA
SWITCHING WAVEFORMS
GND
VCC
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MC74HC374A
50%
tsu
Figure
Figure 3.
1
1
3
3
50%
5 VALID OUTPUT ENABLE th VCC Volts 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 Q Q - 55 to 25_C Min 5.0 5.0 5.0 5.0 60 23 12 10 50 40 10 9 50% 50% 50% 1000 800 500 400 MaxIII Min Max GND VCC GND VCC tPZL tPZH
Figure 2.
Guaranteed Limit 5.0 50 5.0 5.0 75 27 15 13 65 50 13 11 tPHZ v 85_C tPLZ 1000 800 500 400 10% Min 90% 5.0 5.0 5.0 5.0 90 32 18 15 75 60 15 13 v 125_C 1000 800 500 400 Max HIGH IMPEDANCE VOH VOL HIGH IMPEDANCE GND VCC Unit ns ns ns ns
MC74HC374A
TEST CIRCUITS
TEST POINT OUTPUT DEVICE UNDER TEST CL* DEVICE UNDER TEST TEST POINT OUTPUT 1 kW CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
CL*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 4.
Figure 5.
D0 3 D C Clock 11 Q
D1 4 D C Q
D2 7 D C Q
D3 8 D C Q
D4 13 D C Q
D5 14 D C Q
D6 17 D C Q
D7 18 D C Q
Output 1 Enable
2 Q0
5 Q1
6 Q2
9 Q3
12 Q4
15 Q5
16 Q6
19 Q7
Figure 6. Expanded Logic Diagram
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MC74HC374A
PACKAGE DIMENSIONS
PDIP-20 N SUFFIX PLASTIC DIP PACKAGE CASE 738-03 ISSUE E
-A-
20 1 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
B
10
C
L
-T-
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
DIM A B C D E F G J K L M N
INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040
MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
SOIC-20 DW SUFFIX CASE 751D-05 ISSUE G
D
A
11 X 45 _
q
H
M
B
M
20
10X
0.25
E
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
1
10
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
h
18X
e
A1
T
C
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L
MC74HC374A
PACKAGE DIMENSIONS
TSSOP-20 DT SUFFIX CASE 948E-02 ISSUE B
K REF
M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
20X
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
2X
L/2
B L
PIN 1 IDENT 1 10
J J1
-U-
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
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IIII IIII IIII
SECTION N-N M DETAIL E
20
11
K K1
0.25 (0.010)
-W-
DIM A B C D F G H J J1 K K1 L M
MC74HC374A
PACKAGE DIMENSIONS
SOEIAJ-20 F SUFFIX CASE 967-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.81 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.032
20
11
LE Q1 M_ L DETAIL P
E HE
1
10
Z D e VIEW P A
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC74HC374A
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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MC74HC373A/D

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